(1) Field of the Invention
The present invention relates to a display device, and in particular, to a display device where thin film transistors are formed on a substrate.
(2) Related Art Statement
In active matrix type liquid crystal display devices, for example, thin film transistors are formed of switching elements in pixel regions on a substrate.
In this case, it is preferable for the formed thin film transistors to be of a so-called bottom gate type, with gate electrodes provided on the substrate side of the semiconductor layer, with a gate insulating film in between. This is because the gate electrodes function as a light shielding film, the semiconductor layer can be prevented from being irradiated with light from the backlight, and thus, thin film transistors having little leaked current resulting from light can be formed.
In addition, a so-called multi-gate structure has come to be used in bottom gate type thin film transistors, where a number of thin film transistors are formed, and the semiconductor layer is divided into individual regions for each thin film transistor. In thin film transistors having a multi-gate structure, the off current can be reduced by lowering the concentration of the electrical field between the drain region and the channel region.
Furthermore, this structure usually has an LDD (lightly doped drain) region where the impurity concentration is lower than in the channel region and the drain region between the channel region and the drain region, as well as between the channel region and the source region, in the semiconductor layer of each thin film transistor. The LDD regions can lower the concentration of the electrical field, which can be easily generated between the drain region and the channel region in the semiconductor layer, and are easy to form in bottom gate type tin film transistors, without increasing the number of manufacturing steps.
FIG. 8 is a cross sectional diagram showing the configuration of a thin film transistor formed in the display device described above. The thin film transistor TFT in FIG. 8 is formed of a first thin film transistor TFT1 and a second thin film transistor TFT2, which have a semiconductor layer PS which is divided into individual regions. In this case, the portion at approximately the center of the above described semiconductor layer PS is a common region CMD shared by the source region SD of the first thin film transistor TFT1 and the drain region DD of the second thin film transistor TFT2. In addition, the gate electrode of the first thin film transistor TFT1 (denoted by GT1 in figure) and the gate electrode of the second thin film transistor TFT 2 (denoted by GT2 in figure) are separately formed on the substrate SUB1 side of the above described semiconductor layer PS with the gate insulating film GI in between (but electrically connected to each other). In FIG. 8, the symbol DD is for drain regions, the symbol SD is for source regions, and the symbol LD is for LDD regions. This is all for the structure in FIG. 8. This structure is described in further detail below, in order to describe the structure shown in FIG. 1, which corresponds to FIG. 8.